发明名称 |
Zero thermal budget manufacturing process for MOS-technology power devices |
摘要 |
A zero thermal budget manufacturing process for a MOS-technology power device. The method comprises the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; removing the insulated gate layer from selected portions of the semiconductor material layer surface; implanting a first dopant of a second conductivity type into the selected portions of the semiconductor material layer, the insulated gate layer acting as a mask and the first dopant of the first conductivity type being implanted in a dose and with an implantation energy suitable to obtain heavily doped regions substantially aligned with the edges of the insulated gate layer; implanting a second dopant of the second conductivity type along directions at prescribed angles with respect to a direction orthogonal to the semiconductor material layer surface, the insulated gate layer acting as a mask, the second dopant being implanted in a dose and with an implantation energy suitable to obtain lightly doped channel regions extending under the insulated gate layer; and implanting a third dopant of the first conductivity type into the heavily doped regions, to form source regions substantially aligned with the edges of the insulated gate layer.
|
申请公布号 |
US6140679(A) |
申请公布日期 |
2000.10.31 |
申请号 |
US19970856109 |
申请日期 |
1997.05.14 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.R.L.;CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO |
发明人 |
FERLA, GIUSEPPE;FRISINA, FERRUCCIO |
分类号 |
H01L21/265;H01L21/336;H01L29/10;H01L29/78;(IPC1-7):H01L29/76;H01L29/94;H01L31/113;H01L31/119 |
主分类号 |
H01L21/265 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|