发明名称 |
Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol |
摘要 |
A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag or local lock address registers for each individual locked address. Integrity of locked data is accomplished by insuring that load-locked and store-conditional instructions are processed in order, that no internal agents can evict blocks from a local cache as a side effect as their processing, that external agents update the context of cache memories first using invalidating probe commands, and that only non-speculative instructions are permitted to generate external commands. |
申请公布号 |
US6141734(A) |
申请公布日期 |
2000.10.31 |
申请号 |
US19980017752 |
申请日期 |
1998.02.03 |
申请人 |
COMPAQ COMPUTER CORPORATION |
发明人 |
RAZDAN, RAHUL;WEBB, JR., DAVID ARTHUR JAMES;KELLER, JAMES;MEYER, DERRICK R.;LEIBHOLZ, DANIEL LAWRENCE |
分类号 |
G06F12/08;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|