| 摘要 |
PURPOSE: A variable gain amplifier is provided for a power gain to have a linearity without a control signal from the outside. CONSTITUTION: In a variable gain amplifier, a primary P-channel metal oxide semiconductor(PMOS) transistor(MP1) has a drain connected to a node A, and impress a primary direct current(DC) biasing voltage(Vc1) on a gate, and a source voltage(VDD) on a source. A secondary PMOS transistor(MP2) has a drain connected to the node A, and impress a secondary DC biasing voltage(Vc2) on the gate, and a source voltage(VDD) on the source. A primary N-channel metal oxide semiconductor(NMOS) transistor(MN5) has a drain connected to the node A, and impress a positive DC(Vdc+) on the gate. A secondary NMOS transistor(MN7) impresses a positive input voltage(Vin+) on the gate and has a drain connected to the source of the primary NMOS transistor (MN5), and a source which is grounded. A third PMOS transistor(MP3) has a drain connected to a node B, and impress the secondary DC biasing voltage(Vc2) on the gate, and a source voltage(VDD) on the source. A fourth PMOS transistor(MP4) has a drain connected to the node B, and impress a primary direct current(DC) biasing voltage(Vc1) on the gate, and a source voltage(VDD) on a source. A third ENMOS transistor(MN6) has a drain connected to the node B, and impress a negative DC voltage(Vdc-). A fourth NMOS transistor(MN8) impresses a negative input voltage(Vin-) on the gate, and has a drain connected to the source of the third NMOS transistor(MN6), and a source which is grounded. The node A and B outputs an output signal(Voutn)(Voutp).
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