发明名称 |
Process technology architecture of embedded DRAM |
摘要 |
Embedded DRAM cells within an ASIC having a pass transistor with a gate oxide having a thickness equal to the thickness of the gate oxide of the logic core. This allows the embedded DRAM cell to be activated by signals having voltage levels equal to the voltage levels created by the logic core. If the gate oxide has a thickness that is equal to the gate oxide thickness of the peripheral circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by peripheral circuits, and signal provided by the bit line voltage generator has voltage levels equal to those provided by logic circuits within the logic core. If the gate oxide has a thickness that is equal to the thickness of the gate oxide of the logic circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by the logic circuits, and the bit line voltage generator has voltage levels equal to those provided by the logic circuits.
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申请公布号 |
US6136638(A) |
申请公布日期 |
2000.10.24 |
申请号 |
US19980195653 |
申请日期 |
1998.11.19 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
LEE, JIN-YUAN;LIANG, MONG-SONG |
分类号 |
G11C11/4074;H01L21/8238;H01L27/108;(IPC1-7):H01L21/823;H01L21/824;H01L21/336 |
主分类号 |
G11C11/4074 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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