| 摘要 |
PROBLEM TO BE SOLVED: To quickly attain pattern data plotting with low power consumption, and to reduce the operation load of a CPU by providing a decode means or the like for simultaneously validating the writing of the plural memory cells of a display memory in response to an instruction from a host controller(CPU). SOLUTION: A read/write address from a CPU is inputted through a data bus 1 to a CPU interface circuit 101, and at the time of CPU display memory access, a row address 109 is selected by a selector 116 according to a row address selection signal 117. Then, a selected row address 118 is inputted to a row address decoder 125, and one of corresponding word lines 126 is selected. Thus, it is possible to perform access to the prescribed pixel of a display memory 121, and to read and write display data. Thus, the number of times of access to a liquid crystal driver LSI of the CPU is reduced so that pattern data plotting can be quickly attained with low power consumption, and the load of the CPU can be reduced.
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