发明名称 THE METHOD AND APPARATUS FOR CACHE COHERENCE OF MULTIPROCESSOR SYSTEM HAVING DISTRIBUTE SHARED MEMORY STRUCTURE
摘要 PURPOSE: A method and an apparatus for maintaining a cache coherency of a multi-process system having a distributed shared memory is provided to enhance a performance of a system by referring multiple nodes at one time through a bus in a read and write mode in a cache coherency maintaining protocol method. CONSTITUTION: A directory(114) of each node is constructed in a pull map structure, and a cache state of a cache memory(112) of each node with respect to a data block is applied by 1-bit per node, and a cache state is indicated as one among a unshared, shared and dirty state. The directory indicates the entire node(n) and "u" represents a bit used. A source ID separates a start node for a certain transaction and is driven on a bus at the first period of the transaction. Only 1-bit is driven except for the concurrent transmission transaction. When the read operation is performed in a certain processor of the fist node(110), a node(initiator) which starts a read operation is the first node(110), it is checked that there is not a corresponding address in the memory(112) and request a read to the second node(120) having a corresponding address. The second node(120) which receives the read request checks the cache state of a corresponding address. If the third node(130) has a dirty block, a write back is requested with respect to a corresponding address. The information(source ID) of the first node(110) which starts the read operation is informed.
申请公布号 KR100268812(B1) 申请公布日期 2000.10.16
申请号 KR19970069585 申请日期 1997.12.17
申请人 LG ELECTRONICS INC. 发明人 KIM, YONG
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
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