发明名称 |
Low power clock buffer with shared, clocked transistor |
摘要 |
A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-down transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. This circuit may be found useful in clock buffering applications.
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申请公布号 |
US6127850(A) |
申请公布日期 |
2000.10.03 |
申请号 |
US19990346108 |
申请日期 |
1999.06.30 |
申请人 |
INTEL CORPORATION |
发明人 |
LAN, JIANN-CHERNG JAMES;KUMAR, SUDARSHAN |
分类号 |
H03K19/173;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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