发明名称 |
Memory supporting multiple address protocols |
摘要 |
The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined as rows of the memory array designated for storage of data. The decoders decode a memory access requested for the data. The memory access request may be in either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array, a decoder, a control, and a logic gate. The decoders decode a memory access request to select a row of memory array. The control has an output for outputting either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical "Exclusive Or" of the control signal and a corresponding bit of the memory access request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.
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申请公布号 |
US6119226(A) |
申请公布日期 |
2000.09.12 |
申请号 |
US19980076693 |
申请日期 |
1998.05.12 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
SHIAU, TZENG-HUEI;CHEN, HAN-SUNG;CHANG, TSO-MING;WAN, RAY LIN;SHONE, FUCHIA |
分类号 |
G06F9/445;G11C8/00;G11C16/08;G11C16/10;(IPC1-7):G06F9/445 |
主分类号 |
G06F9/445 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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