Arrangement for phase matching of data signal to clock signal in digital integrated circuit, e.g. for mobile telephones and software radio

摘要

The arrangement has an adaptive delay stage (D) for delaying the data signal w.r.t. the clock signal, at least three bistable flip-flop stages (FF1-FF3), a first comparator stage (XOR1) connected to the outputs of the first and second bistable stages, a second comparator stage (XOR2) connected to the outputs of the second and third bistable stages and a control stage (C) connected after the comparator stages. The control stage evaluates the comparator output signals and controls the data signal delay. The first, second and third bistable stage data inputs are respectively the delayed data signal, the data signal delayed by a second delay element (T2) and the data signal delayed by a further second delay element (T2); their clock inputs all receive the clock signal.