Mechanism for resetting sense circuitry to a known state in a nonvolatile memory device

摘要

A memory device including a nonvolatile memory cell, a bit line coupled to the nonvolatile memory cell, and circuitry coupled to the nonvolatile memory cell and the bit line. The circuitry is configured to reset the bit line to a predetermined state for an amount of time in response to a transition of an input address signal.