发明名称 BUS BRIDGE FOR ORDERING WRITING OPERATION
摘要 PROBLEM TO BE SOLVED: To enable the minimum delay for maintaining the proper order of producer consumers and to extend a bus bridge to one-to-many bus bridge configuration. SOLUTION: This bus bridge 50 provides an interface between two computer buses and suitably puts the order of writing operation from one bus to reading operation from the other bus. The bus bridge 50 is provided with a writing/ reading FIFO storage area 42 for counting up the number of times of writing operation to be waited for in the area 42, a PPC 54 for counting the number of times of writing operation received by the area 42, a CPC 56 for counting up the number of times of writing operation completed on the 2nd bus, a CLA counter 58 for measuring the transmission time of data stored in respective cache lines, and ordering logic 62 for delaying the completion of reading operation from a cache.
申请公布号 JP2000235543(A) 申请公布日期 2000.08.29
申请号 JP19990331526 申请日期 1999.11.22
申请人 HEWLETT PACKARD CO <HP> 发明人 DEREK A SHARROCK;THOMAS V SPENCER;FRANCISCO KORERA
分类号 G06F12/08;G06F13/36;(IPC1-7):G06F13/36 主分类号 G06F12/08
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