CIRCUIT FOR MONITORING WORDLINE ACTIVATION DELAY USING SAMPLE WORDLINES ARRANGED IN DATA-STORING ARRAY

摘要

PURPOSE: A circuit for monitoring activation delay using sample wordline arranged in data-storing array is provided to determine wordline activation delay for a first subarray group in a memory by activating sample wordlines arranged in the data-storing array of a second subarray group. CONSTITUTION: A multiple bank memory(10), such as a DRAM, comprises a couple of memory units(12) provided with column decoder/sense amplifiers(19). Each memory unit(12) is determined as a memory domain comprising a memory array accessed by a set of row decoder/row control circuit in a rib(14) of the multiple bank memory(10). A first memory unit(12) comprises 4 banks(16a-16d) and a second memory unit(12) and 4 banks(16e-16h). Each bank has a plurality of sub arrays(18) and is determined as a memory domain which provides access to a plurality of data words. Each subarray(18) is determined as a bank array domain divided from other subarray by a first column decoder/sense amplifier.