| 摘要 |
A multi-path sigma-delta modulator (40) has a sample and hold (S/H) section (41) that converts a received analog signal (25) into quadrature and in-phase signals (45,46) and first and second sigma-delta A/D converter stages (52,53) coupled to the S/H section (41) to convert the respective quadrature and in-phase signals into digital output signals, wherein the S/H section (41) and the sigma-delta A/D converters (52, 53) are controlled by non-overlapping clocks wherein the duration of the S/H clock (P1) is shorter than the duration of the sigma-delta A/D converter stage clocks (P2A,P2B).
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