| 摘要 |
PROBLEM TO BE SOLVED: To reduce the ratio of the resistance of a source and a drain electrode to the total on-state resistance of a transverse field effect transistor(FET). SOLUTION: When executing a pattern layout of a horizontal FET 200 on a semiconductor chip 1, a resistance of source and drain electrodes 201, 202, 207, 208 included in the total on-state resistance Ron between a source pad 211 and a drain pad 212 is expressed as a function of (k), where (k) is the ratio of a horizontal size X to a longitudinal size Y of a cell section of a transistor, and then Ron is subjected to partial differentiation with respect, to (k) to find out (k) which makes Ron minimum. Thereby, when making a cell region S identical to conventional one, the total on-state resistance can be reduced, and when making the total on-state resistance the same as the conventional one, the cell area S can be reduced.
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