Semiconductor memory device equipped with column decoder outputting improved column selecting signals and control method of the same

摘要

PCT No. PCT/JP95/02658 Sec. 371 Date Aug. 18, 1997 Sec. 102(e) Date Aug. 18, 1997 PCT Filed Dec. 25, 1995 PCT Pub. No. WO97/23877 PCT Pub. Date Jul. 3, 1997In a semiconductor memory circuit 100 according to the present invention, a column decoder 103 outputs column selecting signals to column lines (CL), whose output part is formed of inverter (125). A driving potential to be supplied to the inverter is set lower than a power supply potential Vcc supplied from outside. With this arrangement, a timing at which a bit line is connected to a data bus is determined by an amplification rate of a potential on the bit line, thereby providing the semiconductor memory device which performs a high speed and reliable operation.