| 摘要 |
PROBLEM TO BE SOLVED: To cope with a finer semiconductor device and faster operation frequency by automatically generating the pattern of a bypass capacitor so as to overlap the pattern of a power-source wiring after generation of layout of a power-source wiring, etc. SOLUTION: A layout comprising a cell 6, having an MIS structure and patterns of power-source wirings 5a, 5b, and 5c and ground wirings 1a, and 1b, is generated at a semiconductor substrate 7. The dimension of a bypass capacitor is determined based on a design rule and the number of arrays of bypass capacitor which can be arranged is calculated according to design role, and the bypass capacitor array of that array is generated under the ground wirings 1a and 1b. Logical calculations for extraction, resizing, and bypass capacitor arrangement of the power-source wirings 5a, 5b, and 5c are performed, for resizing bypass capacitors. Logical calculation for generating a connecting diffusion layer is performed for resizing. Thus, the pattern of bypass capacitor is automatically generated so as to overlap the pattern of power-source wiring. |
