DEVICE AND METHOD FOR PHASE LOCKED LOOP WHICH SYNCHRONIZING AT HIGH SPEED

摘要

PURPOSE: A phase locked loop device synchronizing at a high speed is provided to maintain the phase noise characteristics excellently by operating the PLL synchronization at a high speed. CONSTITUTION: A phase detector(202) detects a phase difference between a reference frequency and a feedback oscillation frequency and outputs a DC voltage. A voltage controlled oscillator(204) changes the oscillation frequency by the DC voltage detected from the phase detector(202). A memory(212) stores voltage data controlling the voltage controlled oscillator corresponding to a range of a tuning frequency. A microprocessor(206) reads the voltage controlled data, calculates a code value corresponding to the tuning frequency, and synchronizes the reference frequency and the feedback oscillation frequency.