| 摘要 |
PURPOSE: A semiconductor memory device of a layer bit line type is provided to restrain the generation of excessive current in a main bit line while sharing the bank selecting lines by the adjacent bank areas. CONSTITUTION: A word line(WL132) and bank selecting lines(BS12,BS14) are activated while selecting bank cells(TB11,TB17) including a memory cell(M4). Subsidiary bit lines(SB14,SB15) are connected to main bit lines(MB2,MB1) through the bank cells. Herein, a subsidiary bit line(SB25) is connected to the main bit line through a bank cell(TB27). The banks(BNK0,BNK2) adjacent to a bank(BNK1) are included in a different word line group from the bank(BNK1) for activating no word line. Therefore, the excessive current does not flow, and the load of the main bit line is not increased. Thus, an access delay is prevented.
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