LINEAR SAMPLING SWITCH

摘要

A sampling circuit is constructed with a p-channel and an n-channel field effect transistor (FET). A source node of the p-channel FET (42) is coupled to a drain node of the n-channel FET (40) and a drain node of the p-channel FET (42) is coupled to a source node of the n-channel FET (40). A sampling clock is coupled to the gate node of each FET. A first side of the linear sampling circuit is connected to an analog or RF signal source and a far side of the linear sampling circuit is connected to a holding capacitor (44). The n-channel FET has an n-channel width. A p-channel FET has a p-channel width. The p-channel width is larger than the n-channel width in order to increase the linearity of the on-resistance of the resulting switch.