| 摘要 |
<p>PROBLEM TO BE SOLVED: To suppress the power consumption of an instruction cache memory. SOLUTION: The instruction cache memory 12 is provided with a clock gate circuit 26 which controls the supply of a clock signal CLK to a tag RAM 22. This clock gate circuit 22 supplies the clock signal CLK to the tag RAM 22 only when a cache line where a word to be read out is stored is changed or when a processor 14 detects a branch instruction. Consequently, the power consumption of the tag RAM 22 can be suppressed.</p> |
