SERIES AND PARALLEL INTERFACE

摘要

PURPOSE: A series and parallel interface is provided to change the transmission method from series to parallel or from parallel to series, according to the situation of a transmitting/receiving system. CONSTITUTION: A shift register shifts the series data according to the clock signal. And a base register stores the fixed lower four bits of the shift register according to the first control signal. A offset register stores the fixed upper bits of the shift register of the second control signal. Then the comparison part compares whether the stored data of the base register and the set data are same or not and generates the signal of results. And a control part generates the first and the second control signal. A decoder decodes the address signal. A data register stores the parallel data. A first multiplexer selects the address stored in the base and offset register or the decoder and outputs the address. And A second multiplexer selects the stored data in the shift register or the stored data in the data register according to the selected signal and outputs the data.