| 摘要 |
PURPOSE: A method for fabricating a full CMOS SRAM cell is provided to decrease the number of conductive layers and to reduce fabrication cost. CONSTITUTION: In a full CMOS cell wherein PMOS transistors are formed on a silicon substrate, the fabrication begins with a formation of a p-well, an n-well, and a field oxide(11) in the substrate. Next, a gate oxide layer(13) and a first polysilicon layer are formed, and then a gate(Q3) and a word line(P1) are formed from a selective etch of the first polysilicon layer. Next, after sidewall spacers(14) and source/drain regions(12) are formed, a nitride layer(15) covers overall surfaces and a first interlayer dielectric(16) is formed thereon. Then, the nitride layer(15) and the first dielectric(16) are selectively etched to form holes for local interconnection wiring(18A) and power supply(18B). At this time, the nitride layer(15) stops the etching, and therefore the spacers(14) are not damaged. Next, a metal layer such as tungsten is formed and selectively etched to form the local interconnection wiring(18A) and the power supply(18B). Next, a second interlayer dielectric(19) and bit lines(20) are formed.
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