| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption of a shift register and to reduce the occupancy area of chips. SOLUTION: By providing gate circuits 11, 12 for guaranteeing minimum delay in same phase transfer to a second flip-flop circuit (FF-4) from a first flip-flop circuit (FF-2), the arrangement of a flip-flop circuit operating based on a clock signal, of which the phase is different from that of a clock signal supplied to them is dispensed with between the first flip-flop circuit and the second flip-flop circuit, thereby, reduction of power consumption of a shift register and reduction of the occupancy area by chips are achieved. |
