发明名称 System and method for simulating signal flow through a logic block pattern of a real time process control system
摘要 <p>A testing system for, and method of, simulating signal flow through a logic block pattern of a real time process control system. The system includes: (1) a memory that contains a data base of input data associated with simulated sensors and a rule base containing control rules and constituting a logic block pattern and (2) a processor that operates in an arbitrary time base to apply the input data to the control rules to simulate signal flow through the logic block pattern and thereby produce simulated output data and real time control system responses thereby testing the logic block pattern, the memory and the processor being detached from the real time process control system to prevent use of resources thereof in connection with the logic block pattern testing.</p>
申请公布号 AU721795(B2) 申请公布日期 2000.07.13
申请号 AU19970043545 申请日期 1997.09.17
申请人 HONEYWELL INC. 发明人 WILLIAM S. LEIBOLD
分类号 G05B13/02;G05B19/04;G05B19/042;G05B19/418;(IPC1-7):G05B19/042 主分类号 G05B13/02
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