| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a timing or control circuit that realizes a defined relation in advance by using a delay specific to a driver adopting a clock tree configuration. SOLUTION: An input clock signal 62 on a line 62 is propagated to a 1st clock tree 70, from which outputs are given through a plurality of output lines (70 to 75). The input clock signal is also fed to a combination purpose logic circuit 90, which combines the input clock signal with an output of the 1st clock tree 70 to generate an intermediate signal. An output of the combination purpose logic circuit 90 is given to a 2nd clock tree 80, which gives outputs to a plurality of lines (81-85). The output signal from the 1st clock tree is propagated to a logic circuit 95 through the line 71 and the output signal from the 2nd clock tree is propagated to the logic circuit 95 through the line 81.</p> |
