发明名称 SYNCHRONIZING CIRCUIT FOR NON-SYNCHRONIZING SIGNAL AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a synchronizing circuit for non-synchronizing signal, capable of synchronizing a nonsynchronizing signal in a short time, while avoiding unstable output state from flip-flops in the synchronizing circuit comprising plural flip-flops. SOLUTION: This synchronizing circuit is provided with a lock inhibit circuit CIV composed of a circuit OPG for forming a one-shot pulse by detecting the change of an asynchronous input signal with the cascade connection of two flip-flops, having clock terminals and signal input terminals and a transmission gate G3 for controlling the supply of a clock signal to a first stage flip-flop FF1, while using the one-shot pulse as an inhibit signal.</p>
申请公布号 JP2000172637(A) 申请公布日期 2000.06.23
申请号 JP19980348968 申请日期 1998.12.08
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 HISANAGA MASAAKI;YAMAMOTO EIJI
分类号 G06F1/12;G06F13/42;H03K3/037;H04L7/04;(IPC1-7):G06F13/42 主分类号 G06F1/12
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