Peripheral structure for monolithic power device, comprising front and rear surfaces with cathode and anode connections, reverse and forward biased junctions, and insulating wall

摘要

The peripheral structure for a monolithic power device (C1) comprises an n-type conductivity substrate, front and rear surfaces (F1,F2) with cathode and anode connections (10,20), respectively, two junctions (13,23) reverse-biased and forward-biased, respectively, when a direct voltage is applied between anode and cathode, and at least one insulating wall (2) in the form of a peripheral p-type conductivity region connecting the front and the rear surfaces (F1,F2), separated from both junctions. When a direct or a reverse voltage is applied between the anode and the cathode generating equipotential voltage lines, the insulating wall enables a distribution of equipotential voltage lines in the substrate (1). The insulating box is constituted by an insulating wall or barrier (2) in the form of a strongly doped p-type region, and adjacent weekly doped p-type regions (16,26), also adjacent to the respective surfaces (F1,F2). The structure (C1) also comprises weakly doped p-type regions (15,25) adjacent to the first and second junctions (13,23), and also adjacent to the respective surfaces (F1,F2) at middistance between the surfaces. In the second embodiment, a field plate covers the total rear surface (F2) of the structure. In the third embodiment, a field plate covers the total rear surface (F2), and another field plate covers a part of the front surface (F1) between the cathode connection and the region (16) adjacent to the insulating wall (2). The weakly doped regions (15,25) adjacent to the junctions (13,23) are of the JTE (Junction Termination Extension) type. The structure (C1) is preferably planar, and symmetric with respect to a plane (F4) perpendicular to the surfaces (F1,F2) and the plane of the substrate (1). The front and rear surfaces (F1,F2) are covered with the field oxide layers (12,22), excluding the zones of junctions (13,23) and including the zonse of insulating wall (2). In the second and third embodiments, the field oxide layers are interposed between the respective surfaces (F1,F2) and the field plates.