发明名称 PEAK CURRENT LIMIT DETECTING CIRCUIT AND CLASS D AMPLIFIER WITH LOAD IMPEDANCE DETECTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a simple and easy method for limiting current by detecting eddy current in MOSFETs, reducing a gain of an amplifier according to the detected eddy current and thus, reducing outputted current until peak current is reduced to a specified level. SOLUTION: An eddy current limiting circuit 200 is provided with transistors 213, 212, an inverter 15 and a resistor RCL and compresses the gain of a class D modulator 100 by controlling the current into an adding junction of an integrator 10. Technology to perform current control is utilized in an OCL circuit 200. An acoustic signal is converted into the current by the resistor RIN and provided in the adding junction of the integrator. Effective input current to flow to adding junction of the integrator or to flow from the adding junction is reduced and compressed by the gain. The transistors 213, 212, the inverter 15 and the resistor RCL as current limiting elements are operated to reduce the gain and the current.
申请公布号 JP2000165154(A) 申请公布日期 2000.06.16
申请号 JP19990328483 申请日期 1999.11.18
申请人 INTERSIL CORP 发明人 PULLEN STUART;WITLINGER HAROLD
分类号 H03F1/52;H03F3/217;(IPC1-7):H03F1/52 主分类号 H03F1/52
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