发明名称 |
Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline |
摘要 |
A data processor is disclosed which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to the pipelines, a first set of registers being coupled with the first pipeline, and a second set of registers being coupled with the second pipeline, wherein first and second pipeline process data in parallel. |
申请公布号 |
US6076159(A) |
申请公布日期 |
2000.06.13 |
申请号 |
US19970928766 |
申请日期 |
1997.09.12 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
FLECK, ROD G.;MOLLER, OLE H.;BAROR, GIGY |
分类号 |
G06F9/30;G06F9/38;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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