发明名称 PROCESSOR SYSTEM BUS
摘要 PROBLEM TO BE SOLVED: To improve the transmission efficiency of a processor system bus by providing a means which detects only one of peripheral devices transferring an instruction or data to a bus and a means which sends a NACK from among one of the one peripheral device, and enabling the one peripheral device to transfer the instruction or data successively in each bus cycle. SOLUTION: Peripheral devices 5 to 7 which are desired of transfer instructions or data send requests to a request, instruction, or data line 3. Then all the peripheral devices 5 to 7 are arbitrated, to decide a peripheral device to acquire the right to use the bus. The peripheral device having obtained the right transfers instructions or data. Other peripheral devices must decode and accept the instructions or data. If they are in an acceptable state instructions or data are processed, but if they are state which cannot be accepted, NACK is sent in the next bus cycle.
申请公布号 JP2000148666(A) 申请公布日期 2000.05.30
申请号 JP19980343595 申请日期 1998.11.17
申请人 NEC ENG LTD 发明人 KITADA KATSUYA
分类号 G06F13/36;G06F13/00;(IPC1-7):G06F13/36 主分类号 G06F13/36
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