| 摘要 |
PROBLEM TO BE SOLVED: To reduce such a burden on a user that the user must rearrange VHDL(very high-speed IC hardware design language) sources by programming the arranging procedure of the sources. SOLUTION: The hierarchical order of VHDLs which are manually arranged in the conventional example is automatically analyzed 11 by making a VHDL simulator analyze the order. Since the VHDL simulator is provided with a function of basically checking syntaxes, in this case, the simulator is made to make rearranging processing 10 for rearranging VHDL sources in the hierarchical order in such a way that the simulator checks the names of individual VHDL sources and the names of the children VHDL sources (sources of lower hierarchies) of the individual VHDL sources by utilizing the function and rearranging the sources from those having no children.
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