| 摘要 |
A digital signal transmission apparatus, wherein at the time of normal data transmission, an output circuit of a transmitter unit selects transmission data SDAT and converts it to a differential signal for output to the transmission line, while a clock recovery circuit of the receiver unit generates a clock signal LCK matching the frequency of the transmission clock signal TCK and receives the signal based on the same. When the clock signal LCK and the received signal deviate in frequency, the clock reproduction circuit outputs a common mode reference clock request signal to the transmission line. In accordance with this, the transmitter unit selects the reference clock signal RCK for output to the transmission line. The clock recovery circuit of the receiver unit uses this to make the frequency of the clock signal LCK match the transmission clock signal. As a result, it is possible to handle a wide range of transmission rates, it is possible to quickly track a transmission clock when a reproduced clock signal deviates from a transmission clock signal, and it is possible to simplify the circuit configuration and reduce the space taken by the transmission line.
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