| 摘要 |
<p>In order to provide a PLL circuit constituted of only one digital loop filter and adapted to multiple reproduction channel rates, when the channel rate of the reproduced signal reproduced by a reproducing device (1) changes at a rate which is n/m of the basic channel rate of recording, a reproduction clock is generated by frequency-dividing the output of a voltage-controlled oscillator (7) oscillating at the basic channel rate by n/m by means of a frequency divider (6). Thus the reproduction clock adapted to the reproduction signal is realized by means of only one voltage-controlled oscillator (7). The control signal controlling the voltage-controlled oscillator (7) is generated through a phase difference detector (3) and a digital loop filter (4). The digital loop filter (4) processes a signal by using the reproduction clock of which the frequency is n/m of the output of the voltage-controlled oscillator (7). As a result, even if the reproduction channel rate changes at the n/m rate, the frequency characteristics change analogously with it, and a PLL circuit is realized which has the same loop delay and loop sensitivity even at any data rate.</p> |
