| 摘要 |
In a multilevel interconnection structure for a semiconductor device, lower level interconnections 3 are formed on an insulator film 2 formed on a substrate 1, and a silicon oxide film 4a is formed to cover the lower level interconnections 3 and to fill up a region between adjacent lower level interconnections 3, by means of a biased ECR-CVD process so that a cavity 5 is formed in the silicon oxide film 4a between the adjacent lower level interconnections 3. The silicon oxide film 4a is selectively removed from a tolerable region covering the extent in which a hole for the metal pillar 6 is allowed to deviate from a target lower level interconnection 3, and then, another silicon oxide 4b is formed to fill up the removed portion and to cover the first silicon oxide film. The metal pillar 6 is formed to extend through the silicon oxide film 4b filling the removed portion of the silicon oxide film 4a, so as to reach the target lower level interconnection 3. On the metal pillar 6, an upper level interconnection 7 is formed. Thus, since the cavity 5 is completely surrounded by the silicon oxide film 4a, a contact between the cavity 5 and the metal pillar 6 is completely prevented by the silicon oxide film 4a. <IMAGE> |
