SYSTEM AND METHOD FOR INPUTTING TIMING SPECIFICATION OF LOGIC CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide environment wherein timing analysis and logic composition can accurately and easily be performed by easily inputting the timing specifications of the circuit at a function description stage without any omission. SOLUTION: An inter-facility connection information storage part 11 is a file containing connection information between facilities by the layers of the circuit and a facility indication part 12 takes registers in a specified module out of the inter-facility connection information storage part 11 and displays them on a screen so that a register whose connection relation should be found will be indicated. An inter-front-and-rear-stage-facility display part 13 takes the connection information of the indicated register out of the inter-facility connection information storage part 11 and displays it on the screen. An inter- facility timing specification input part 14 allows the number of cycles and whether or not there is a corresponding false path to be inputted on the screen. Then a timing specification description generation part 15 converts information inputted on the screen to a VHDL description and inserts it into a function description stored in a specification description storage part 16.