Methods for making high-aspect ratio holes in semiconductor and its application to a gate damascene process for sub- 0.05 micron mosfets

摘要

The present invention provides a process of fabricating high aspect ratio holes (H/L is 2 or greater) in a semiconductor structure wherein a masked gate-like reactive ion etch process is employed. The high aspect ratio holes have perfectly vertical sidewalls thus they are particularly useful in fabricating gate electrodes of sub-0.05 mu m MOSFETs using a damascene process.