| 摘要 |
PROBLEM TO BE SOLVED: To obtain a drive pulse with a low-frequency clock and a frequency high resolution by setting the average frequency-division ratio of a specific cycle period nearly equal to a value that is obtained by dividing specified bit data being outputted from a frequency-setting circuit by a specific value, and setting the fluctuation of the frequency-division ratio within the specific cycle period to a specific value or less. SOLUTION: An error voltage is outputted in synchronism with a smoothing cycle period from an error voltage operation circuit 8 in synchronism with a master clock, and the error voltage and a current frequency setting value are added and outputted in synchronism with pulses with only different delay timings at the same cycle as the smoothing cycle pulse in a frequency setting circuit 9. The outputted data is the upper three-bit data (frequency division ratio) of data (five bits) being outputted from each frequency setting circuit 9 and the lower two-bit data (dispersion). The number of dispersion is set by the lower two bits out of the five-bit data being outputted from the frequency setting circuit 9 since the number N of dispersion is equal to four. An operation is made so that the clock cycle of the four cycle periods of a drive pulse being obtained by frequency division becomes equal to a frequency setting value, thus improving average frequency resolution. |
