| 摘要 |
PURPOSE: A flash memory device is provided to decrease a disturbance by a stress provided to a drain and a gate by decreasing a bias time provided to a reference cell while a data read operation is performed. CONSTITUTION: An X-decoder and a Y-decoder decode an inputted address and selects a memory cell of a memory cell array. A sense amplifier(41) senses a current amount of the memory cell selected by the X-decoder and the Y-decoder and a reference cell. A reference cell bias voltage control circuit(40) controls a voltage biased to the reference cell. A data latch unit(42) stores a data amplified in a sense amplifier. An input and output buffer outputs the data stored in the data latch unit(42). The reference cell bias voltage control circuit(40) has a timer(401) for generating a control pulse with a high level according to an address transition detecting signal with a high level, and is operated according to a set clock period, an inverter(402) for inverting a control pulse, an NOR gate(403) for outputting a high level signal in the case that input signals are all low level, first and second NMOS transistors(N41,N42), and first and second PMOS transistors(P41,P42).
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