| 摘要 |
PURPOSE: A dynamic buffer circuit is provided to reduce a chip size and an interference by a noise signal generated in an external supply voltage. CONSTITUTION: The dynamic buffer circuit includes a differential amplifier(101) and a comparison voltage generator(102). The differential amplifier inputs an external input signal(EXT_IN) and a comparison voltage, amplifies the difference of the two input signals in response to an enable signal(ENABLE) and outputs the first and second signals(OUT,OUT1). The comparison voltage generator generates the comparison voltage in response to the external input signal. The comparison voltage generator has an inverter(G6) of a static buffer type, a voltage divider circuit(MN10,MP6,MP7) and a PMOS transistor(MP5). The enable signal is a clock signal. When the external input signal is a logic high, the comparison voltage becomes a logic low and then the differential amplifier outputs a logic high. When the external input signal is a logic low, the comparison voltage becomes a logic high.
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