发明名称 D-RAM INTERFACING DEVICE OF PDP TELEVISION
摘要 PURPOSE: A dynamic RAM interface apparatus of a PDP television is provided to load and output data to a DRAM by using a memory element of the DRAM for storing video information, and by providing a line buffer unit in the front of the DRAM. CONSTITUTION: A line buffer unit(100) receives an NTSC composite video signal, and temporarily stores an R/G/B color signal digitalized and outputted. A PISO unit(110) rearrays data in serial. A memory unit(120) is composed of an A DRAM(120a) and a B DRAM(120b) which store the R/G/B data outputted from the PISO unit(110). A data selection unit(130) reads data relevant to an address applied from a DRAM address generator(150), and outputs the data. A PDP(140) displays the R/G/B data outputted from the data selection unit(130). A line buffer control unit(170) is connected to the line buffer unit(100), and controls the buffer(100). A load clock and shift pulse generator(160) generates a load clock and a shift pulse. A DRAM address generator(150) provides an address needed to the memory unit(120). A vertical position setting device(180) inputs valid data and a vertical synchronous signal, and applies a vertical position pulse to the line buffer unit(170).
申请公布号 KR100256499(B1) 申请公布日期 2000.05.15
申请号 KR19970052404 申请日期 1997.10.13
申请人 DAEWOO ELECTRONICS CO.,LTD. 发明人 PARK, JUN-SEOK
分类号 H04N5/66;(IPC1-7):H04N5/66 主分类号 H04N5/66
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