| 摘要 |
PROBLEM TO BE SOLVED: To improve an arithmetic speed in a recovery system requiring an arithmetic operation with high accuracy especially in an expanded PRML by dividing part or all of values used in an arithmetic operation in an adder/ comparison circuit section into n-sets of bit strings depending on their digit positions and arranging the arithmetic results. SOLUTION: The adder/comparison circuit consists of an added circuit ADD 101, an adder circuit ADD 102 and a comparison circuit CMP 103. Two values to be summed are divided into higher-order bit strings A(3:2) and B(3:2) and low-order bit strings A(1:0) and B(1:0), and they are independently calculated. The comparator circuit CMP 103 consists of two comparison circuits, an AND circuit and an OR circuit. In this case, the two comparison circuits discriminate which of two values is larger or both of which are equal to each other, based on two input values and a carry input from the lower-order bits.
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