INTERNAL CLOCK SIGNAL GENERATION CIRCUIT, PHASE COMPARATOR, AND METHOD FOR TESTING INTERNAL CLOCK SIGNAL GENERATION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide an internal clock signal generation circuit which establishes phase synchronization at an early stage while suppressing a layout area and insures a stable operation. SOLUTION: This internal clock signal generation circuit consists of a small delay stage 10 which changes delay quantity in a minute way and a delay stage 20 which changes delay quantity on a large scale. The stage 10 responds to a control? signal R(0)... outputted by a control circuit 50, and performs fine adjustment of delay quantity. The stage 20 includes plural inherent delay circuits that realize comparatively large delay. An inherent delay circuit to be connected to the stage 10 is selected based on the control of the circuit 50. Thus, it is possible to apply the circuit to frequencies in a wide range in a very small area.