| 摘要 |
A computer aided design (CAD) method for verifying the layout of an integrated circuit (IC), in which the capacitance of a selected wiring network in the layout, is calculated, in relation to other wiring layouts (networks) contained in the layout, such that a filter polygon is determined to correspond in shape to the selected wiring network. The dimensions of the filter polygon are increased by a specific amount relative to those of the selected wiring network, and the elements of the other wiring network which overlap with the filter polygon are determined. The capacitance between the selected wiring network and the elements of the other wiring network overlapping with the filter polygon, is then determined.
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