| 摘要 |
<p>In a DMA control apparatus which is connected to a bus system for transferring a lowest digit address from an even address when a data is transferred on a bus having a plurality of byte bus widths using a bus width of more than or equal to two bytes, the apparatus has transfer size determining means 14 for, every data transfer, obtaining optimum transfer byte size which is a bus width during a data transfer on a bus, based on address regions and transfer byte numbers of a transfer source and a transfer destination. <IMAGE></p> |
