APPARATUS FOR PREVENTING LATCH-UP WITHIN PMOS TRANSISTOR AND NMOS TRANSISTOR

摘要

PURPOSE: An apparatus for preventing latch-up within a PMOS transistor and an NMOS transistor is provided to prevent latch-up in a MOS type IC by using a parasitic diode. CONSTITUTION: An apparatus for preventing latch-up within a PMOS transistor and an NMOS transistor comprises an amplifier(302), a comparator(304), and a switch(306). The amplifier receives a first voltage and a second voltage and generates a first amplified voltage and a second amplified voltage. The comparator combined with the amplifier compares the amplified first voltage and the amplified second voltage and generates larger one of them as a control signal. The switch combined with the comparator larger performs an inverse bias for a parasitic diode by connecting larger voltage to an N well.