Deposition chamber with a biased substrate configuration

摘要

Disclosed is PVD deposition chamber which is modified with an electrical circuit that allows a voltage bias to be applied to any one or more of a target, an in-process integrated circuit wafer, and collimator. The collimator can also be isolated from the electrical circuit. This configuration allows a preclean of the in-process integrated circuit wafer in situ in the PVD deposition chamber by ion sputtering and a subsequent sputter deposition through the collimator. A method is also disclosed wherein an in-process integrated circuit wafer is first precleaned in the PVD deposition chamber by applying a negative voltage bias to the in-process integrated circuit wafer. A film of conducting material is then sputter deposited on the surface of the in-process integrated circuit wafer by applying a negative voltage bias to the target. The collimator is electrically isolated during this process or is set at a higher potential than the in-process integrated circuit wafer. A voltage bias can also be applied to the in-process integrated circuit wafer during the deposition, and its magnitude proportioned to modify the morphology of the film being deposited. Once the deposition is conducted, a negative voltage bias can be applied to the collimator to sputter clean the collimator.