Phase-locked loop which can automatically adjust to and lock upon a variable input frequency

摘要

An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another. By modifying the frequency division factor, the PLL can dynamically lock upon a changed input signal frequency without varying the clocking signal output from the PLL. Thus, the PLL can accommodate various input signal frequencies yet maintain a relatively fixed clocking signal to be forwarded as a timing reference to a digital processor.