| 摘要 |
PROBLEM TO BE SOLVED: To surely mute output signals if a processing is not completed within a prescribed time period while digital signals are being processed in a block unit. SOLUTION: In this digital signal processor(DSP), a data inputting and a computational process are conducted in a block unit in accordance with one period of signals BLCK(A). The processed data are outputted in a next one period. Computation completion flags (B) are sampled by the signals BLCK using a D-flip-flop(D-FF), which becomes a low level at the beginning of a computation and becomes a high level at the completion of the computation. As a result, it is shown that the computation is not completed with a high level (C). Thus, the data of the next one period are not outputted because the computations are not completed (D). For example, by taking an AND of the sampling output and the output of the DSP, the output data of the DSP is mute controlled (E). Thus, the processing capability of the DSP is maximally used. |
