发明名称 TEST PATTERN GENERATOR EMBEDDING CIRCUIT
摘要 PURPOSE: A test pattern generator embedding circuit is provided to confirm whether a connection state between a television and display machine is normal or whether the television and the display machine are normal. CONSTITUTION: The circuit is configured using a pixel counter and a horizontal synchronous counter when realizing a test pattern in a set-top-box product having a video output. A test pattern circuit is configured by use of an output of an analog component fashion. In a video product, after generating a test pattern signal using the EPLD, the test pattern signal is merged to an analog component output so as to be formed a complex signal.
申请公布号 KR20000018005(A) 申请公布日期 2000.04.06
申请号 KR20000000103 申请日期 2000.01.04
申请人 AZ TECHNOLOGY CO., LTD. 发明人 PARK, HEUNG MU
分类号 H04N17/00;(IPC1-7):H04N17/00 主分类号 H04N17/00
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