DRAM CELL SYSTEM AND METHOD FOR PRODUCING SAME

摘要

Word lines (5, 6) and bit lines (8, 9, 10) are positioned above a main surface (H) of a substrate (S) in such a way that they present a planar structure and can be produced together with gate electrodes of transistors on a periphery of the cell system. For each memory cell a cavity (V) is provided for in the substrate (S) which in its lower part has a memory node (K) of a memory capacitor and in its upper part a gate electrode of a vertical transistor. The cavities (V) of the memory cells are positioned between trenches filled with separating structures (T). Upper source/drain areas (S/D1) of the transistors are positioned between two adjacent separating structures (T) and between two adjacent cavities (V). Lower source/drain areas (S/D2) are positioned in the substrate (S) and adjoin the memory nodes (K). For process steps calibration tolerances are set such that the space requirement per memory cell can be as much as 4F<2>.